Job Description

A rapidly expanding, high-speed focused client in the bay area looking to grow their presence. They are seeking a Senior RTL Design Engineer to join their growing ASIC Design Team.

Expereince:

• Senior RTL Design Engineer with experience in Architecting/designing/integrating PCIe Root Complex, Host Bridge, Root Port, Address Translation Service and IOMMU for Server side PCIe Root Complex functionality.
• Ability to use IPs from standard vendors and Architect/Design any missing logic modules to be able to integrate with rest of the ASIC modules in the Server SoC ASICs.
• A thorough understanding of System level functionality and how PCIe Root Complex modules integrate with Cache-Coherent NoCs, Memory Subsystems, CPU complexes through AMBA bus protocols is required.
• Also, need to design and integrate CXL.io and CXL.mem functionality into the Root Complex and Root Port Modules by configuring the IPs from Standard Vendors like Synopsys.
• Work with our design and verification teams spread across Armenia, India, China, and the backend/PR team located in China.

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